A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter

Abstract We present a 5-order continuous-time Σ∆ modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time Σ∆ modulator with 2MHz signal bandwidth is designed in a 0.25μm CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype Σ∆ modulator achieves 68dB dynamic range over 2MHz bandwidth with a 150MHz clock, consuming 1.8mA from a 1.5V supply.